Circuit designers use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to create a functional circuit design, including a register transfer level (RTL) representation of the functional circuit design, synthesize a “netlist” from the RTL representation, and implement a layout from the netlists. Synthesis of the netlist and implementation of the layout involve simulating the operation of the circuit and determining where cells should be placed and where interconnects that couple the cells together should be routed. EDA tools allow designers to construct a circuit, simulate its performance, estimate its power consumption and area and predict its yield using a computer and without requiring the costly and lengthy process of fabrication.
One such EDA tool performs equivalence checking. Equivalence checking is a part of the EDA process typically used during the development of circuits to formally prove that two representations of a circuit design exhibit exactly the same behavior. One form of equivalence checking is comparing an RTL of a circuit design to a netlist developed from the RTL.